In the design of semiconductor memory devices, attention is continually given to simplifying circuits utilized in connection with such devices. Simplified circuits typically require less space, consume less power, and operate more reliably than more complicated circuits. However, as the speed at which such memory devices operate increases, complexity of circuit designs used in connection with such devices tends to increase.
For example, in a typical semiconductor memory device, such as an SRAM, DRAM, PROM, EPROM, or the like, a change in an address supplied to the device causes data previously output from the device to become invalid after some typically short specified period of time. When the device is being operated at maximum speed, the address changes as soon as the output data becomes valid. Consequently, data remains valid at the device output for only a short period of time. The device is difficult to utilize when operated at maximum speed because the data output does not remain valid for an acceptably long period of time. Moreover, as device speed increases, a precharge portion of an access cycle tends to occur more quickly after an address change, and this rapid precharge tends to further decrease valid data output time.
One solution to this shrinking valid data output time problem has been to incorporate a latch in a memory device. However, the timing and control circuitry used in connection with such a latch tends to be undesirably complicated. The complication arises due to a very critical timing requirement in capturing valid data and to a very critical timing requirement in connection with releasing data so that a subsequent access cycle will not be delayed by operation of the latch.
In addition, many semiconductor memory devices tolerate a certain amount of crowbar current in connection with data transitions at output buffers of the memory devices. Crowbar current represents a current surge which flows between power rails through the output buffer. It typically results from momentary, simultaneous activation of two, series connected active devices located between the power rails. These current surges are undesirable because they cause excess power consumption and because they produce voltage surges within the memory device. As memory device speed increases, internal circuitry tends to become more susceptible to the undesirable effects of such voltage surges. Consequently, circuit complexity tends to increase to ensure that such surges are minimized and to ensure that such surges do not adversely affect the circuits.
One solution to the crowbar current problem has been to utilize differences in rise and fall times of the circuits driving the active devices to deactivate one of the tWo active devices a very short amount of time before beginning to activate the second of the two active devices. However, this solution is undesirable because the insubstantial timing difference tends not to significantly reduce crowbar currents, and because these relative activation and deactivation rates can reverse in the presence of radiation or at extreme temperatures.
Consequently, a need exists for a simple circuit which addresses the valid output data time and crowbar current problems.